1. Technical Field
The invention relates to computer systems. More particularly, the invention relates to a method and apparatus for ensuring data consistency between an I/O channel and a processor in a computer system.
2. Description of the Prior Art
In prior art computer systems, an input/output (I/O) adapter (also referred to as a channel) performed read and write operations to memory. This approach was inefficient. Accordingly, modern prior art I/O adapters include a cache to improve system memory latency and bandwidth for direct memory access (DMA) transactions. In servicing DMA requests, an I/O adapter considers a request to be completed once the cache is updated. The cache is then kept coherent. In most cases, this protocol is acceptable.
However, in some computer systems, such as the PA-RISC architecture manufactured by Hewlett-Packard Company of Palo Alto, Calif., processor data requests are coherent, i.e. all caches in the system are effectively checked to see where the most up-to-date copy of a particular piece of data is located, but in such systems, processor instruction requests, e.g. fetching code instructions, are considered to be non-coherent because the contents of the instructions should not be modifiable. Thus, the system software is designed to force coherency only in the event that the instructions are modified. Accordingly, instruction requests read whatever is in memory. As a result, instruction requests can be serviced faster than comparable data requests because coherency does not have to be checked.
Unfortunately, a problem arises when there is a DMA sequence that writes a series of instructions into memory, i.e. where the instructions are first written into the memory's cache. In such case, the system tells a processor, typically via an interrupt transaction, that it has finished the DMA sequence. If the processor then branches to the newly written series of instructions, the non-coherent read might find a previous (i.e. stale) version of the data in memory if the new DMA version of the data is still in the I/O adapter's cache.
One method of solving this problem is to make the instruction read transaction a coherent transaction, so that it is able to find the new DMA version in the I/O adapter's cache. However, this approach slows down all other instruction read transactions.
Another method of solving this problem is to modify the I/O adapter so that it writes any modified line from its cache to memory when it receives a notification of DMA completion. However, this technique is difficult to implement because there are several different ways that an I/O device can notify a processor that a DMA sequence is complete, and one of those ways itself resembles a portion of a DMA sequence.
It would be advantageous to provide a method and apparatus that ensures data consistency between an I/O channel and a processor without unnecessarily complicating computer system operation and/or degrading computer system performance.